Transistors are commonly used in semiconductor circuitry to control current flow. For example, a transistor can be used as a switching mechanism to allow the flow of current between a source and a drain region in a circuit when a certain threshold voltage is met. Transistors generally include a gate electrode that allows or prevents the flow of current in the transistor based on applied voltage.
FIG. 1a shows a cross-sectional view of a conventional gate electrode 100 formed on a substrate 110, the underlying structure of which is not shown. It should be noted that the figures are merely illustrative and have been simplified for clarity purposes. A thin insulative layer 120 is formed on the substrate 110 to act as a barrier between the substrate 110 and the conductive portions of the gate electrode 100. An example of an insulative layer 120 can be an oxide layer, such as silicon dioxide (SiO.sub.2). Formed on the insulative layer 120 is a gate layer 130.
An example of a gate layer 130 can be a polysilicon layer. Formed on the gate layer 130 is a conductive layer 160. For example, a conductive layer 160 can be a polycide layer, such as titanium salicide (TiSi.sub.2). When a threshold voltage is applied to the gate layer 130 by the conductive layer 160, current will flow through the gate layer 130. Often insulative spacers 140 and 150 are formed to each side of the gate layer 130 to prevent transfer of current between the gate layer 130 and surrounding structures in the semiconductor.
In semiconductor circuit design, frequently, gate electrodes are designed in long continuous lines on the semiconductor substrate to efficiently provide current to several transistors in a circuit. Currently, improved semiconductor transistor performance is being achieved through device scaling in which the gate layer widths are being reduced from 0.20 .mu.m to 0.15 .mu.m and below (sub-0.15 .mu.m). As the gate layer width dimensions decrease, so do the conductive layer line widths formed above them.
When the gate layer widths decrease below 0.20 .mu.m, current process techniques produce conductive lines with sharply increasing resistance. This is detrimental to the efficiency of the semiconductor, as higher resistance decreases the speed of the semiconductor circuitry. Additionally, process yields drop due to defective conductive line formation reducing manufacturing output. These problems have been particularly noted in current fabrication processes where titanium salicide (TiSi.sub.2) is formed as the conductive layer in a polysilicon gate.
FIG. 1b illustrates a cross-sectional view of a conventional gate electrode 100 formed on a substrate 110, the underlying structure of which is not shown. An example of a gate electrode 100 can be a polysilicon gate electrode. Formed on the substrate 110 is an insulative layer 120. An example of an insulative layer 120 can be an oxide. Formed on the insulative layer 120 is a conductive gate layer 130. An example of a gate layer 130 is a polysilicon layer. Formed on the gate layer 130 is a conductive layer 160. For example, a conductive layer 160 can be a polycide, such as titanium salicide (TiSi.sub.2). Insulative spacers 140 and 150 are formed adjacent to the gate layer 130 and conductive layer 160 to prevent current flow between the gate layer 100 and surrounding structures.
During formation of the conductive layer 160, components from underlying gate layer 130 often out diffuse into a reactant layer that is used to form the conductive layer 160. For example, silicon components of an underlying gate layer 130 may out diffuse into the conductive layer 160. This out diffusion results in a conductive layer 160 wider than the gate layer 130. When the gate layer 100 width is decreased below 0.20 .mu.m, the conductive layer 160 becomes stressed by its enclosure between the side walls of the spacers 140. This results in increased resistance in the conductive layer 160. Increased resistance in the conductive layer directly impacts the quality of the semiconductor circuit. The circuit becomes inefficient and circuit failure or device failure may occur.
Another result of decreasing the gate line widths below 0.20 .mu.m is a decrease in process yields. This is due to non-formation of the conductive layer. This is attributed to the reduced reaction area, or nucleation sites, available at such small dimensions. The reduced dimensions of the gate layer reduce nucleation sites on which the conductive layer can form during processing. Using current process techniques, if sufficient nucleation sites are not provided, the conductive layer often won't form. This directly impacts the semiconductor manufacturer by reducing output.
Based on the above-described problems, it would be desirable to have a method and/or device that will improve the polycide resistance in polysilicon gate widths below 0.20 .mu.m.